1. Field of Invention
The present invention is related to a synchronous receiver IC and, more particularly, to the synchronous receiver solving the uncertain-arrival-time problem.
2. Background of The Related Art
In high-speed IC, the delay variation among ICs made has become significantly large compared to the period of clock signal in the IC. The large delay variation may result from many factors, such as the manufacture process variation, operating voltage variation, temperature variation, clock-signal skew, clock-signal jitter or input loading variation. It is difficult to maintain the signal arrival time within one clock period of a high frequency synchronous system. So the destination side might wait for multiple clocks to receive data. This situation causes chip function to fail.
Please refer to FIG. 1, which illustrates two subsystems with data delay latency of M clocks and delay variation of m clocks. The source and destination clock tracks for transmitter 102 and receiver 100 are ideally balanced. Then the signal arrival time is determined by the data delay latency and the delay variation. As the data delay latency is 6 ns and the delay variation is 2 ns, then the signal arrival time falls between 4 ns and 8 ns, there is no problem for the receiver 100 to detect input data correctly if the clock period is 10 ns. But when the clock period is 5 ns, an arrival time varying between 4 ns and 8 ns results in sampling the wrong data on the receiver 100. If the receiver 100 is designed to sample the signal in the first clock period, the designer must control the signal arrival time to be within 0 to 5 ns. If the receiver 100 is designed to sample the signal in the second clock, the designer must control the signal arrival time to be within 5 ns to 10 ns. Above is the case that delay variation is smaller than the clock period.
When the delay variation is larger than the clock period, the method mentioned above does not work. So the designer must deal with variation control, which cannot be easily done in a high frequency system. The present invention discloses a multiple-stage FIFO mechanism in a receiver capable of handling large delay variation range and providing an efficient way to detect data with uncertain delay.